1. Field of the Invention
This invention relates to processors, and more particularly, to cache memories in processors.
2. Description of the Related Art
Cache memories figure prominently in the performance of computer system processors. As processor technology has advanced and the demand for performance has increased, the number and capacity of cache memories has followed. Some processors may have a single cache or single level of cache memory, while others may have multiple levels of caches. Some cache memories may be used for storing data, while other cache memories may be used for storing instructions, while some may store both. Cache memories for storing other types of information (e.g., address translations) are also used in some processors.
Cache memories may be defined by levels, based on their proximity to execution units of a processor core. For example, a level one (L1) cache may be the closest cache to the execution unit(s), a level two (L2) cache may be the second closest to the execution unit(s), and an level three (L3) cache may be the third closest to the execution unit(s). When accessing information (e.g., an operand) for an instruction to be executed, an execution unit may first query the L1 cache. If the information is not stored in the L1 cache (i.e., a cache miss), the L2 cache may be queried, and so forth. If the information is not stored in any cache, the information may be accessed from other storage such as main memory or from disk storage. Since the latency associated with memory and disk storage accesses is much greater than the latency associated with cache accesses, cache memories have become larger to accommodate more data and/or instructions. However, these larger cache memories may consume more power than their smaller counterparts. Accordingly, some processors may remove power to part or all of a cache memory when the processor is idle.